Architectural Synthesis Via

Signature ARCHITECTURAL SYNTHESIS VIA VHDL A library based behavioral synthesis tool for digital systems is presented in this thesis. The library based synthesis tool, called TinkerTool, integrates an architectural synthesis tool, SandS, i n to the Keystone design environment. The synthesis tool provides a means by which a designer can conceive and conngure complex designs in a behavioral language and generate hierarchical VHDL for simulation. The synthesis tool performs speeddarchitectureearea trade oos based on accurate estimates of the nal circuit. This allows designers to take a black b o x" approach to design for any well deened design style. A major impact of this hierarchical component approach is that representations, other than VHDL, can be attached to a component. For example, mask layout of the entire design could be constructed by using layouts attached to each subcomponent. Such hierarchical layout generation would be much faster than current at transistor level layout generation.